View ADP3408_973895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES Handles All GSM Baseband Power Management 6 LDOs Optimized for Specific GSM Subsystems Li-Ion and NiMH Battery Charge Function Optimized for the AD20msp430 Baseband Chipset APPLICATIONS GSM/DCS/PCS/CDMA Handsets
GSM Power Management System ADP3408
FUNCTIONAL BLOCK DIAGRAM
VBAT VBAT2 VRTCIN SIM LDO DIGITAL CORE LDO ANALOG LDO POWER-UP SEQUENCING AND PROTECTION LOGIC TCXO LDO MEMORY LDO RTC LDO REF BUFFER
VSIM
VCORE
PWRONKEY ROWX PWRONIN
VAN
VTCXO
TCXOEN
VMEM
GENERAL DESCRIPTION
The ADP3408 is a multifunction power system chip optimized for GSM handsets, especially those based on the Analog Devices AD20msp430 system solution. It contains six LDOs, one to power each of the critical GSM subblocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end-of-charge signal when a Li-ion battery is being charged. The ADP3408 is specified over the temperature range of -20C to +85C and is available in a narrow body TSSOP 28-lead package or 5 mm 5 mm LFCSP 32-lead package.
SIMEN RESCAP
VRTC
26 REFOUT
RESET
CHRDET EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN BATTERY CHARGE CONTROLLER
BATTERY CHARGE DIVIDER
MVBAT
DGND
ADP3408
27 AGND
(Pin Assignment Is for TSSOP Option)
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
+85 VBAT = VBAT2 3 CVCORE = CVAN ADP3408-SPECIFICATIONS1 (-2010C F,TminimumC,loads applied on=all V-5.5 V, CVSIM =otherwise noted.) = CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = outputs, unless
A
Parameter
SHUTDOWN SUPPLY CURRENT VBAT 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT 3.2 V (UVLO Active) VBAT > 3.2 V OPERATING GROUND CURRENT VSIM, VCORE, VMEM, VRTC On All LDOs On
Symbol
ICC
Condition
VBAT = VBAT2 = 2.3 V VBAT = VBAT2 = 3.0 V VBAT = VBAT2 = 4.0 V
Min
Typ
7 30 45 225 345 1.0
Max
20 55 80 300 450 3.0
Unit
A A A A A % of max load current V mV
IGND
VBAT = 3.6 V Minimum Loads Minimum Loads Maximum Loads
UVLO ON THRESHOLD UVLO HYSTERESIS DEEP DISCHARGED LOCKOUT ON THRESHOLD DEEP DISCHARGED LOCKOUT HYSTERESIS INPUT HIGH VOLTAGE (TCXOEN, SIMEN, CHGEN, GATEIN) PWRONIN (ADP3408-1.8) PWRONIN (ADP3408-2.5) INPUT LOW VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) INPUT HIGH BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) PWRONKEY INPUT HIGH VOLTAGE PWRONKEY INPUT LOW VOLTAGE PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT THERMAL SHUTDOWN THRESHOLD2 THERMAL SHUTDOWN HYSTERESIS ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current SIM CARD LDO (VSIM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage DIGITAL CORE LDO (VCORE) Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Line Regulation Load Regulation Output Capacitor Required for Stability
VBAT VBAT VBAT VBAT VIH 2.0 1.1 2.0 VIL
3.2 200 2.4 100
3.3
2.75
V mV
V V V 0.3 V
IIH
1.0
A
IIL
-1.0
A
VIH VIL
0.7
VBAT 0.3
V VBAT V 130 k C C
70
100 160 45
VOL IIH
PWRONKEY = Low IOL = 200 A PWRONKEY = High V(ROWX) = 5 V Line, Load, Temp Min Load 50 A ILOAD 20 mA, VBAT = 3.6 V VO = VINITIAL - 100 mV, ILOAD = 20 mA 2.80 2.85 2 1
0.4 1 2.92
V A V mV mV F
VSIM VSIM VSIM CO VDO
2.2 35 100
mV
VCORE VCORE VCORE VCORE CO
Line, Load, Temp Line, Load, Temp Min Load 50 A ILOAD 100 mA, VBAT = 3.6 V
2.40 1.75
2.45 1.80 2 7
2.50 1.85
V V mV mV F
2.2
-2-
REV. A
ADP3408
Parameter
RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC) Maximum Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Off Reverse Input Current Output Capacitor Required for Stability ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage
Symbol
Condition
Min
Typ
Max
Unit
VRTC VRTC IL CO VAN VAN VAN CO VBAT/ VAN VNOISE
1 A ILOAD 10 A 1 A ILOAD 10 A VBAT = 2.15 V, TA = 25C
2.39 1.80 0.1
2.45 1.95
2.51 2.1 0.5
V V A F V mV mV F dB
Line, Load, Temp Min Load 50 A ILOAD 130 mA, VBAT = 3.6 V f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 130 mA VBAT = 3.6 V
2.40
2.45 2 8
2.50
2.2 65 80
V rms
TCXO LDO (VTCXO) Output Voltage ADP3408-2.5 ADP3408-1.8 Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage
VTCXO VTCXO VTCXO VTCXO CO VDO VBAT/ VTCXO VNOISE
Line, Load, Temp Line, Load, Temp Min Load 50 A ILOAD 20 mA, VBAT = 3.6 V VO = VINITIAL - 100 mV ILOAD = 20 mA f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 20 mA, VBAT = 3.6 V Line, Load, Temp Min Load 50 A < ILOAD < 60 mA, VBAT = 3.6 V ILOAD = 60 mA ILOAD = 80 mA
2.66 2.711
2.715 2.750 2 1
2.77 2.789
V V mV mV F mV dB
0.22 160 65 80 310
V rms
MEMORY LDO (VMEM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance
VMEM VMEM VMEM CO
2.744
2.80 2 3
2.856
V mV mV F mV mV V mV mV dB pF V rms
2.2 80 107 1.19 1.210 0.2 0.5 75 180 210 1.23
VREFOUT VREFOUT VREFOUT VBAT/ VREFOUT CO VNOISE
Line, Load, Temp Min Load 0 A < ILOAD < 50 A VBAT = 3.6 V f = 217 Hz VBAT = 3.6 V, ILOAD = 50 A f = 10 Hz to 100 kHz, VBAT = 3.6 V IOH = 500 A IOL = -500 A VOL = 0.25 V, VOH = VMEM - 0.25 V
65 100
40
VOH VOL IOL IOH TD
VMEM - 0.25 0.25 1 1 1.2
0.6
2.4
V V mA mA ms/nF
BATSNS/MVBAT ZO
TCXOEN = High TCXOEN = Low TCXOEN = High
2.32 59.5 215
2.35 85 300
2.37 110 1 385
k A k
REV. A
-3-
ADP3408
Parameter
BATTERY CHARGER Charger Output Voltage
Symbol
BATSNS
Condition
4.35 V CHRIN 10 V3 CHGEN = Low, No Load CHRIN = 10 V CHGEN = Low, No Load 0 C < TA < 50 C CHRIN = 5 V 0 CHRIN - ISENSE < Current Limit Threshold CHGEN = Low
Min
4.150 4.155
Typ
4.200
Max
4.250 4.230
Unit
V V
Load Regulation
BATSNS
15
mV
CHRDET On Threshold CHRDET Hysteresis CHRDET Off Delay4 CHRIN Supply Current BATTERY CHARGER Current Limit Threshold High Current Limit (UVLO Not Active)
CHRIN - BATSNS CHRIN < VBAT CHRIN = 5 V CHRIN - ISENSE CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low 0 C < TA < 50 C VBAT = 2 V CHGEN = Low CHRIN = 5 V CHRIN - ISENSE CHRIN = 5 V DC VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High, GATEIN = High IOH = -1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = -250 A IOL = +250 A CHRIN = 7.5 V CHGEN = High GATEIN = Low CHRIN = 7.5 V CHGEN = High GATEIN = Low
30
90 40 6 0.6
150
mV mV ms/nF mA
142
160
190
mV
149
160
180
mV
Low Current Limit (UVLO Active) ISENSE Bias Current End-of-Charge Signal Threshold
20
35
mV A mV
200 14
35
EOC Reset Threshold GATEDR Transition Time
VBAT t R , tF VOH
3.82 0.1
3.96
4.10 1
V s V
GATEDR High Voltage
4.5
GATEDR Low Voltage
VOL
0.5
V
Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) Battery Overvoltage Protection Threshold (GATEDR High) Battery Overvoltage Protection Hysteresis
VOH VOL BATSNS
2.4 0.25 5.30 5.50 5.70
V V V
BATSNS
200
mV
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125C. Operation beyond 125C could cause permanent damage to the device. 3 No isolation diode present between charger input and battery. 4 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice.
-4-
REV. A
ADP3408
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin with respect to any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +10 V Voltage on any pin may not exceed VBAT, with the following exceptions: CHRIN, GATEDR, ISENSE Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Operating Ambient Temperature Range . . . . . -20C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C JA, Thermal Impedance (TSSOP-28) 4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . 68C/W 2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . 98C/W JA, Thermal Impedance (LFCSP) 4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . 32C/W 2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
ORDERING GUIDE
Model ADP3408ARU-2.5 ADP3408ACP-2.5 ADP3408ARU-1.8 ADP3408ACP-1.8
Core LDO Output Voltage 2.5 V 2.5 V 1.8 V 1.8 V
Temperature Range -20C to +85C -20C to +85C -20C to +85C -20C to +85C
Package Option RU-28 CP-32 RU-28 CP-32
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3408 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
ADP3408
PIN CONFIGURATIONS TSSOP (RU) LFCSP (CP)
32 NC 31 ROWX 30 PWRONKEY
28 TCXOEN 27 AGND
26 REFOUT
PWRONKEY 2 ROWX 3 SIMEN 4 VRTCIN 5 VRTC 6 BATSNS 7 MVBAT 8 CHRDET 9 CHRIN 10 GATEIN 11 GATEDR 12 DGND 13 ISENSE 14
27 AGND 26 REFOUT 25 VTCXO 24 VAN
SIMEN 1 VRTCIN 2 VRTC 3 BATSNS 4 MVBAT 5 CHRDET 6 CHRIN 7 GATEIN 8 GATEDR 9
25 VTCXO 24 NC 23 VAN 22 VBAT 21 VCORE 20 VMEM 19 VBAT2 18 VSIM 17 NC RESET 16
PWRONIN 1
28 TCXOEN
ADP3408
ARU
23 VBAT 22 VCORE 21 VMEM 20 VBAT2 19 VSIM 18 RESET 17 RESCAP 16 CHGEN 15 EOC
PIN 1 INDICATOR
(Not to Scale) TOP VIEW
ADP3408 TOP VIEW ACP
NC 10 DGND 11 ISENSE 12
29 PWRONIN
EOC 13 CHGEN 14
PIN FUNCTION DESCRIPTIONS
TSSOP Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
LFCSP Pin 29 30 31 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 18 19 20 21 22 23 25 26 27 28 10, 17, 24, 32
Mnemonic PWRONIN PWRONKEY ROWX SIMEN VRTCIN VRTC BATSNS MVBAT CHRDET CHRIN GATEIN GATEDR DGND ISENSE EOC CHGEN RESCAP RESET VSIM VBAT2 VMEM VCORE VBAT VAN VTCXO REFOUT AGND TCXOEN NC
Function Power On/Off Signal from Microprocessor Power On/Off Key Power Key Interface Output SIM LDO Enable RTC LDO Input Voltage Real-Time Clock Supply/Coin Cell Battery Charger Battery Voltage Sense Input Divided Battery Voltage Output Charge Detect Output Charger Input Voltage Microprocessor Gate Input Signal Gate Drive Output Digital Ground Charge Current Sense Input End of Charge Signal Charger Enable for GATEIN, NiMH Pulse Charging Reset Delay Time Main Reset SIM LDO Output Battery Input Voltage 2 Memory LDO Output Digital Core LDO Output Battery Input Voltage Analog LDO Output TCXO LDO Output Output Reference Analog Ground TCXO LDO Enable and MVBAT Enable No Connection
-6-
RESCAP 15
REV. A
ADP3408
Table I. LDO Control Logic
VAN and REFOUT
PWRONKEY
PWRONIN
CHRDET
TCXOEN
PHONE STATUS
State #1 Battery Deep Discharged State #2 Phone Off State #3 Phone Off, Turn-On Allowed State #4 Charger Applied State #5 Phone Turned On by User Key State #6 Phone Turned On by BB State #7 Enable SIM Card State #8 Phone and TCXO LDO Kept On by BB
L H
X L
X X
X X
X X
L L
X X
OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF
H H
H H
L H
H X
L X
L L
X L
OFF OFF OFF OFF OFF OFF ON ON ON ON
ON ON
OFF OFF
H H H
H H H
X L L
L H H
X H H
L L L
L L H
OFF OFF ON
ON ON ON
ON
ON
ON ON ON
ON ON ON
OFF OFF OFF
OFF OFF OFF OFF
H
H
L
H
H
H
H
ON
ON
ON
ON
ON
ON
ON
*UVLO is active only when phone is turned off. UVLO is ignored once the phone is turned on.
REV. A
-7-
MVBAT
VTCXO
VCORE
UVLO*
SIMEN
VMEM
DDLO
VRTC
VSIM
ADP3408 -Typical Performance Characteristics
450 400 350 ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H, TCXOEN = H)
10000
A REVERSE LEAKAGE CURRENT -
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE - C RTC REVERSE LEAKAGE (VBAT = 2.3V) RTC REVERSE LEAKAGE (VBAT = FLOAT)
-20 C +85 C 1000
300 250 200 150 100 3.0
I VRTC - A
IGND - A
VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L)
+25 C 100
VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L)
10
3.5 4.0 4.5 VBAT - V 5.0 5.5
0
0.5
1.0 1.5 VRTC - V
2.0
2.5
TPC 1. Ground Current vs. Battery Voltage
TPC 2. RTC I/V Characteristic
TPC 3. VRTC Reverse Leakage Current vs. Temperature
180 160
3.2
VTCXO
3.2
DROPOUT VOLTAGE - mV
140 120 100 80 60 40 20 0 0 20 40 60 LOAD CURRENT - mA 80 VSIM VMEM
VBAT 3.0
VBAT 3.0
VTCXO VMEM
10mV/DIV 10mV/DIV
VTCXO VMEM
10mV/DIV 10mV/DIV
TIME - 100 s/DIV
TIME - 100 s/DIV
TPC 4. Dropout Voltage vs. Load Current
TPC 5. Line Transient Response, Minimum Loads
TPC 6. Line Transient Response, Maximum Loads
3.2
3.2
20mA
VBAT 3.0 VAN VCORE VSIM 10mV/DIV 10mV/DIV 10mV/DIV 3.0 VAN VCORE VSIM 10mV/DIV 10mV/DIV 10mV/DIV VBAT
LOAD 3mA
VTCXO
10mV/DIV
TIME - 100 s/DIV
TIME - 100 s/DIV
TIME - 200 s/DIV
TPC 7. Line Transient Response, Minimum Loads
TPC 8. Line Transient Response, Maximum Loads
TPC 9. VTCXO Load Step
-8-
REV. A
ADP3408
100mA
20mA LOAD 3mA
60mA LOAD 5mA
LOAD 10mA
VSIM
5mV/DIV
VMEM 10mV/DIV
VCORE 10mV/DIV
TIME - 200 s/DIV
TIME - 200 s/DIV
TIME - 200 s/DIV
TPC 10. VSIM Load Step
TPC 11. VMEM Load Step
TPC 12. VCORE Load Step
130mA
PWRONIN (2V/DIV) VAN (100mV/DIV)
PWRONIN (2V/DIV) REFOUT (100mV/DIV)
LOAD
10mA
VSIM (100mV/DIV)
VAN 10mV/DIV
VMEM (100mV/DIV) VCORE (100mV/DIV) VTCXO (100mV/DIV)
TIME - 200 s/DIV
TIME - 400 s/DIV
TIME - 100 s/DIV
TPC 13. VAN Load Step
TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1)
TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2)
80
PWRONIN (2V/DIV) PWRONIN (2V/DIV)
70 VAN RIPPLE REJECTION - dB 60
VTCXO
REFOUT (100mV/DIV) VAN (100mV/DIV)
VCORE 50 40 30 20 10 0 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS REFOUT
VSIM (100mV/DIV)
VMEM (100mV/DIV)
VCORE (100mV/DIV) TIME - 20 s/DIV
VTCXO (100mV/DIV) TIME - 20 s/DIV
4
10
100 1k 10k FREQUENCY - Hz
100k
TPC 16. Turn On Transient by PWRONIN, Maximum Load (Part 1)
TPC 17. Turn On Transient by PWRONIN, Maximum Load (Part 2)
TPC 18. Ripple Rejection vs. Frequency
REV. A
-9-
ADP3408
80 70 RIPPLE REJECTION - dB 60 50 40 VTCXO 30 20 10 0 2.5 FREQUENCY = 217Hz MAX LOADS 2.6 2.7 2.8 2.9 3.0 VBAT - V 3.1 3.2 3.3 VMEM VCORE VAN VSIM
VOLTAGE SPECTRAL NOISE DENSITY - nV/ Hz
REFOUT
600 FULL LOAD MLCC CAPS VAN
4.25 4.24 4.23
500
CHARGER VOUT - V
100 1k 10k FREQUENCY - Hz 100k
400
4.22 4.21 4.20 4.19 4.18 4.17 4.16
TCXO
300
200 REF 100
0 10
4.15 -40
-20
0
20
40
60
80
100 120
TEMPERATURE - C
TPC 19. Ripple Rejection vs. Battery Voltage
4.24 VIN = 5.0V RSENSE = 250m
OUTPUT VOLTAGE - V
TPC 20. Output Noise Density
TPC 21. Charger V OUT vs. Temperature, VIN = 5.0 V, ILOAD = 10 mA
4.24 RSENSE = 250m
OUTPUT VOLTAGE - V
4.23
4.23
4.22
4.22
ILOAD = 500mA
4.21
ILOAD = 10mA 4.21
4.20 0 200 400 ILOAD - mA 600 800
4.20 5 6 7 8 INPUT VOLTAGE - V 9 10
TPC 22. Charger VOUT vs. I LOAD (VIN = 5.0 V)
TPC 23. Charger VOUT vs. VIN
-10-
REV. A
ADP3408
VBAT VRTCIN VBAT2 SIM LDO VBAT 100k Q PWRONKEY ROWX S UVLO DEEP DISCHARGED UVLO VREF EN DGND OUT VSIM
R OVER TEMP SHUTDOWN
DIGITAL CORE LDO VBAT VREF EN DGND OUT PG VCORE
PWRONIN
ANALOG LDO VBAT SIMEN CHARGER DETECT TCXOEN RESCAP CHRDET VBAT VREF EN EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN Li-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE MEMORY LDO VBAT VREF EN DGND OUT VMEM AGND OUT VTCXO RESET GENERATOR RESET TCXO LDO VREF EN AGND OUT VAN
RTC LDO VBAT VREF EN DGND OUT VRTC
MVBAT
EN REF BUFFER
REFOUT
ADP3408
1.21V AGND
+ - AGND DGND
Figure 1. Functional Block Diagram (TSSOP Option Pin Number)
EOC CHGEN GATEIN D1 10BQ015 Q1 SI3441DY
ADP3408
BATSNS GATEDR ISENSE BATTERY CHARGE CONTROLLER
R1 0.2
C1 1nF
CHRIN (10V MAX) CHRDET
Figure 2. Battery Charger Typical Application (TSSOP Option Pin Number)
REV. A
-11-
ADP3408
PWRON PWRONKEY KEYPADROW GPIO PWRONIN PWRONKEY ROWX SIMEN VRTCIN VRTC CAPACITOR TYPE BACKUP COIN CELL AUXADC GPIO CHARGER IN GPIO R1 0.33 Q1 SI3441DY D1 10BQ015 Li-ION NIMH BATTERY C2, 1nF GATEDR DGND ISENSE RESCAP CHGEN EOC C4 0.1 F C1 0.1 F VRTC TCXOEN AGND REFOUT VTCXO R2 10 REF VTCXO C3, 10 F VAN C8 2.2 F C9 0.22 F C10 0.1 F VCORE VMEM C6 2.2 F VSIM RESET C5 2.2 F C7 2.2 F GPIO GPIO CLKON
U1
VAN VBAT VCORE VMEM VBAT2 VSIM RESET
ADP3408
BATSNS MVBAT CHRDET CHRIN GATEIN
Figure 3a. Typical Application Circuit (TSSOP Option)
PWRON POWERKEY KEYPADROW 32 31 30 29 28 27 26 25 R2 10 TCXOEN (CLKON) REFOUT VTCXO PWRONIN ROWX AGND NC PWRONKEY TCXOEN REFOUT VTCXO C9 0.22 F C10 0.1 F
GPIO
1 2
SIMEN VRTCIN VRTC BATSNS MVBAT CHRDET CHRIN
NC VAN VBAT
24 23 22 21 20 19 18 17 VSIM C8 2.2 F VAN
VRTC SUPERCAP COIN CELL AUXADC GPIO CHARGER IN GPIO R1 0.33
3 C1 0.1 F 4 5 6 7 8 C2 1nF
U1 ADP3408
VCORE VMEM VBAT2 VSIM
VCORE VMEM
ISENSE
CHGEN
RESCAP
GATEIN DGND NC
GATEDR 9 Q1 SI3441 D1 10BQ015 Li-ION or NiMH BATTERY
11
12
13
15
10
14
16
RESET
NC
EOC
RESET GPIO GPIO C3 10 F C4 0.1 F C5 2.2 F C6 2.2 F C7 2.2 F
Figure 3b. Typical Application Circuit (LFCSP Option)
-12-
REV. A
ADP3408
THEORY OF OPERATION
1.2
The ADP3408 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3408.
POWER DISSIPATION - W
1.0
ADP3408-1.8
The ADP3408 contains several blocks: * Six Low Dropout Regulators (SIM, Core, Analog, Crystal Oscillator, Memory, Real-Time Clock) * Reset Generator * Buffered Precision Reference * Lithium Ion Charge Controller and Processor Interface * Power-On/-Off Logic * Undervoltage Lockout * Deep Discharge Lockout These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3408 combines the benefits of both worlds by providing an integrated standard product in which every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. Figure 3 shows the external circuitry associated with the ADP3408. Only a minimal number of support components are required.
0.8
ADP3408-2.5
0.6
0.4
0.2
0 3.0
3.5
4.0 4.5 5.0 INPUT VOLTAGE - V
5.5
6.0
Figure 4a. Power Dissipation vs. Input Voltage
1.2
1.0
LFCSP 32 C/W
POWER DISSIPATION - W
Input Voltage
0.8 TSSOP 68 C/W 0.6
The input voltage range of the ADP3408 is 3 V to 5.5 V and is optimized for a single Li-ion cell or three NiMH cells. The type of battery, the package type, and the Core LDO output voltage all affect the amount of power that the ADP3408 needs to dissipate. The thermal impedance of the TSSOP package is 68C/W for four-layer boards. The thermal impedance of the CSP package is 32C/W for four-layer boards. The end of charge voltage for high capacity NiMH cells can be as high as 5.5 V. This results in a worst-case power dissipation for the ADP3408-1.8 as high as 1.07 W for NiMH cells. The power dissipation for the ADP3408-2.5 is just slightly lower at 1 W. A fully charged Li-ion battery is 4.25 V, where the ADP34082.5 can dissipate a maximum power of 0.56 W in either package. However, the ADP3408-1.8 can have a maximum dissipation of 0.64 W, so only the CSP package can handle the power dissipation at 85C. However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode, there is a relatively light load on the LDOs. The worst-case power dissipation should be calculated based on the actual load currents and voltages used. Figure 4a shows the maximum power dissipation as a function of the input voltage. Figure 4b shows the maximum allowable power dissipation as a function of ambient temperature.
0.4
0.2
0 -20
0
20 40 60 AMBIENT TEMPERATURE - C
80
Figure 4b. Allowable Package Power Dissipation vs. Temperature
Low Dropout Regulators (LDOs)
The ADP3408 high performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 F tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 F capacitor is recommended for the TCXO LDO.
REV. A
-13-
ADP3408
NON-CHARGING MODE
ripple coming from the RF power amplifier. VAN is rated to a 130 mA load, which is sufficient to supply the complete analog section of the baseband converter, such as the AD652l.
TCXO LDO (VTCXO)
NO
CHARGER DETECTER CHRIN > BATSNS
YES
YES VBAT > UVLO
The TCXO LDO is intended as a supply for a temperaturecompensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 5 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted. Note that for the ADP3408-2.5, the TCXO output has been optimized for the AD6524 (Othello), while the ADP3408-1.8 has been optimized for the AD6534 (Othello One).
RTC LDO (VRTC)
NO LOW CURRENT CHARGE MODE VSENSE = 20mV
NiMH
BATTERY TYPE
Li+
The RTC LDO charges up a capacitor-type backup coin cell to run the Real-Time Clock module. It has been designed to charge electric double layer capacitors such as the PAS621 from Kanebo. The PAS621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 F, giving many hours of backup time. The ADP3408 supplies current both for charging the coin cell and for the RTC module. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module.
SIM LDO (VSIM)
CHGEN = LOW
CHGEN = HIGH
HIGH CURRENT CHARGE MODE VSENSE = 160mV
NiMH CHARGING MODE GATEIN = PULSED
NO
VBAT > 4.2V
The SIM LDO generates the voltage needed for 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs.
Reference Output (REFOUT)
NO VBAT > 5.5V
YES
YES NiMH CHARGER OFF GATEIN = HIGH
CONSTANT VOLTAGE MODE
The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be used with the baseband converter. Note that the reference in the AD6521 has an initial accuracy of 10%, but can be calibrated to within 1%.
Power ON/OFF
NO
ICHARGE < I END OF CHARGE
VBAT < 5.5V
NO
YES EOC = HIGH
The ADP3408 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3408 in three different ways: * Pulling the PWRONKEY Low * Pulling PWRONIN High * CHRIN exceeds CHRDET Threshold Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn on all the LDOs , except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation, the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3408 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/ OFF control. Pulling the PWRONIN pin high is how the alarm in the Real-Time Clock module will turn the handset on. Asserting PWRONIN will turn on the core and memory LDOs, starting up the baseband processor.
YES TERMINATE CHARGE CHREN = HIGH GATEIN = HIGH
Figure 5. Battery Charger Flow Chart
Digital Core LDO (VCORE)
The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads, as this LDO is on at all times.
Memory LDO (VMEM)
The memory LDO supplies the peripheral subsystems of the baseband processor including GPIO, display, and SIM interfaces as well as memory. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO.
Analog LDO (VAN)
This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the
-14-
REV. A
ADP3408
Applying an external charger can also turn on the handset. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs.
Deep Discharge Lockout (DDLO)
re-enabled before the die temperature is below 125C, regardless of the state of PWRONKEY, PWRONIN, and CHRDET. This ensures that the handset will always power-off before the ADP3408 exceeds its absolute maximum thermal ratings.
Battery Charging
The DDLO block in the ADP3408 has two functions: * To shut off the VRTC LDO in the event that the main battery discharges to below the RTC LDO's output voltage. This will force the Real-Time Clock to run off the backup coin cell or double layer capacitor. * To shut down the handset in the event that the software fails to turn off the phone when the battery drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cells.
Undervoltage Lockout (UVLO)
The ADP3408 battery charger can be used with lithium ion (Li+) and nickel metal hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: * Low Current (Trickle) Charging * Lithium Ion Charging * Nickel Metal Hydride Charging
Charge Detection
The UVLO function in the ADP3408 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery voltage is greater than 3.2 V, for example, when inserting a fresh battery, the UVLO comparator trips and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Note that the DDLO has enabled the RTC LDO under this condition. Once the system is started and the core and memory LDOs are up and running, the UVLO function is disabled. The ADP3408 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts off the phone at around 3.0 V. If the handset is off, and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3408 into UVLO shutdown mode. In this mode the ADP3408 draws very low quiescent current, typically 30 A. The RTC LDO is still running until the DDLO disables it. In this mode the ADP3408 draws 5 A of quiescent current. NiMH batteries can reverse polarity if the three-cell battery voltage drops below 3.0 V, which will degrade the batteries' performance. Lithium ion batteries will lose their capacity if repeatedly overdischarged, so minimizing the quiescent currents helps prevent battery damage. RESET The ADP3408 contains a reset circuit that is active at both power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, which starts the reset delay timer. The delay is set by an external capacitor on RESCAP:
tRESET = 1.2 ms x CRESCAP nF (1)
The ADP3408 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 90 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 45 mV above the BATSNS pin, CHRDET goes low.
Trickle Charging
When the battery voltage is below the UVLO threshold, the charge current is set to the low current limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by:
ICHR (TRICKLE ) = 20 mV RSENSE
(2)
Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded, the charger will switch to the default charge mode, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode.
Lithium Ion Charging
For lithium ion charging, the CHGEN input must be low. This allows the ADP3408 to continue charging the battery at the full current. The full charge current can be calculated by using:
ICHR ( FULL) =
160 mV RSENSE
(3)
At power-off, RESET will be kept low to prevent any baseband processor starts.
Overtemperature Protection
The maximum die temperature for the ADP3408 is 125C. If the die temperature exceeds 160C, the ADP3408 will disable all the LDOs except the RTC LDO. The LDOs will not be
If the voltage at BATSNS is below the charger's output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, an Endof-Charge signal is generated and the EOC output goes high. See Figure 6.
REV. A
-15-
ADP3408
VBAT ICHG
Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN.
LDO Capacitor Selection
EOC
The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 F capacitor, and the TCXO LDO requires a 0.22 F capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP(R) technology). The ADP3408 is stable with extremely low ESR capacitors (ESR ~ 0), such as Multilayer Ceramic Capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric capacitor, X7R or better, is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 F ceramic capacitor is recommended for stability and best performance.
RESET Capacitor Selection
TIME
Figure 6. End of Charge
The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high.
NiMH Charging
For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current-limited adapter is required. During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached, at which time the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected.
Battery Voltage Monitoring
RESET is held low at power-up. An internal power good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP: ms x CRESCAP (4) nF A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 A. tRESET = 1.2
Setting the Charge Current
The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT, both PWRONIN and TCXOEN must be high. The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521's auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down.
APPLICATION INFORMATION Input Capacitor Selection
The ADP3408 is capable of charging both lithium ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For lithium ion batteries, the charge current is programmed by selecting the sense resistor, R1. The lithium ion charge current is calculated using: ICHR = VSENSE 160 mV = R1 R1 (5)
Where VSENSE is the high current limit threshold voltage. Or if the charge current is known, R1 can be found.
R1 =
VSENSE 160 mV = ICHR ICHR
(6)
Similarly, the trickle charge current and the end of charge current can be calculated: ITRICKLE = 20 mV 14 mV VSENSE = , I EOC = R1 R1 R1 (7)
For the input (VBAT, VBAT2, and VRTCIN) of the ADP3408, a local bypass capacitor is recommended. Use a 10 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size, but may not be cost effective. A lower cost alternative may be to use a 10 F tantalum capacitor with a small (1 F to 2 F) ceramic in parallel.
Example: Assume an 800 mAh capacity lithium ion battery and a 1C charge rate. R1 = 200 m, ITRICKLE = 100 mA, and IEOC = 70 mA.
anyCAP is a registered trademark of Analog Devices Inc.
-16-
REV. A
ADP3408
Appropriate sense resistors are available from the following vendors: Vishay Dale IRC Panasonic
Charger FET Selection
VDS = V ADAPT ( MIN ) - VDIODE - VSENSE - VBAT = 5V - 0.5V - 0.160 V - 4.2 V = 140 mV 140 mV VDS RDS (ON ) = = = 175 m ICHR ( MAX ) 800 mA
PDISS = V ADAPT ( MAX ) - VDIODE - VSENSE - UVLO x ICHR PDISS = ( 6.5V - 0.5V - 0.160 V - 3.2 ) x 0.8 A = 2.11 W
(
)
The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and charge current. The selected PMOS must satisfy the physical, electrical, and thermal design requirements. To ensure proper operation, the minimum VGS the ADP3408 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following:
VGS = VADAPTER ( MIN ) - VGATEDR - VSENSE
Appropriate PMOS FETs are available from the following vendors: Siliconix IR Fairchild
Charger Diode Selection
(8)
where: VADAPTER(MIN) is the minimum adapter voltage, VGATEDR is the gate drive "low" voltage, 0.5 V, and VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the on resistance of the FET at maximum charge current, where:
VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT
The diode, D1, shown in Figure 2, is used to prevent the battery from discharging through the PMOS's body diode into the charger's internal bias circuits. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3408. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO capacitors should be returned to AGND. 3. VCORE, VMEM, and VSIM capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin-connect the charger's sense resistor by running separate traces to the CHRIN and ISENSE pins. Make sure that the traces are terminated as close to the resistor's body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3408 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance.
(9)
The RDS(ON) of the FET can then be calculated. RDS (ON ) = VDS I CHR ( MAX ) (10)
The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using:
PDISS = VADAPTER (MAX ) - VDIODE - VSENSE - UVLO x I CHR
(
)
(11)
It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case, the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 800 mA VSENSE = 160 mV VGATEDR = 0.5 V VGS = 5 V - 0.5 V - 160 V = 4.34 V Therefore, choose a low threshold voltage FET.
REV. A
-17-
ADP3408
LFCSP Layout Consideration
The CSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. To achieve the optimum performance from the CSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the CSP package: 1. The pad pattern is given in Figure 7. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging.
0.08
The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the large size of the thermal pad, eliminating voids may not be possible. Also, if the solder paste coverage is too large, solder joint defects may occur. Therefore, it is recommended to use multiple small openings over a single big opening in designing the paste mask. The recommended paste mask pattern is given in Figure 9. This pattern will result in about 80% coverage, which should not degrade the thermal performance of the package significantly.
CREATE SOLDER PASTE WEB FOR APPROX. 80% COVERAGE 125 MICRONS WIDE TO SEPARATE SOLDER PASTE AREAS
0.70 5.36 3.80 3.56 3.96
0.30 THERMAL PAD AREA
0.50
0.20
Figure 9. LFCSP Paste Mask Pattern
Figure 7. LFCSP Pad Pattern (Dimensions Shown in Millimeters)
2. The thermal pad of the CSP package provides a low thermal impedance path to the PCB. Therefore, the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 8 for the recommended via pattern. Note that the via diameter is small. This is to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Note that the thermal pad is attached to the die substrate, so the thermal planes that the vias attach the package to must be electrically isolated or connected to VBAT. Do not connect the thermal pad to ground.
ARRAY OF 9 VIAS 0.25mm DIAMETER 35 m PLATING 0.60 1.18 THERMAL PAD AREA 1.18 0.60
5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A "No Clean," Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220 C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3 C/second or lower. The actual temperature profile depends on the board's density and must be determined by the assembly house as to what works best.
Figure 8. LFCSP via Pattern (Dimensions Shown in Millimeters)
3. The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in minimum 60 microns (2.4 mils) clearance between the copper pad and solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. -18- REV. A
ADP3408
OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
Dimensions shown in millimeters
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX
COPLANARITY 0.10
SEATING PLANE
0.20 0.09
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
32-Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 12 MAX 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08
17 16
9
3.50 REF
1.00 0.90 0.80 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. A
-19-
ADP3408 Revision History
Location 11/02--Data Sheet changed from REV. 0 to REV. A Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
C02623-0-12/02(A) PRINTED IN U.S.A.
Page
Note added to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated PIN CONFIGURATIONS added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Figures 1 and 2 captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edit to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to Figure 3 (changed to Figure 3a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3b added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 replaced with Figures 4a and 4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to Input Voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Text added to TCXO LDO (VTCXO) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to RTC LDO (VRTC) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to Reference Output (REFOUT) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to Trickle Charging section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to Equation 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Edit to Settling the Charge Current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Addition of LFCSP Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 New Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 New Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 New Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Add 32-Lead LFCSP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
-20-
REV. A

▲Up To Search▲

Price & Availability of ADP3408

	To Download ADP3408 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .